The present invention relates to memory array devices. More particularly, the present invention relates to the structure and fabrication of memory element layers in non-volatile memory array devices.
Typical non-volatile memory array devices consist of memory cells fabricated on semiconductor substrates. The memory cells in such memory array devices generally consist of memory elements and field effect transistors (FET) electrically coupled to word-lines and bit-lines.
Spin Torque Transfer (STT) Magnetoresistive Random Access Memory (MRAM) is an attractive emerging memory technology, offering non-volatility, high performance and high endurance. The STT MRAM memory cell typically consists of a Magnetic Tunnel Junction (MTJ) in series with a word-line-gated field effect transistor, and with a bit-line at one or both ends. If only one end of the cell is connected to a BL, the other is connected to a mid-level voltage (Vmid). Conventionally, the FET is constructed within a silicon substrate and the MTJ is constructed between two subsequent wiring levels. The contacts, landing pads, and wiring conflicts associated with this structure decrease density, yield and reliability. Additionally, the trend of increasing density presents conflicts with performance, yield and reliability of the memory elements.